Integrated circuits (IC) devices go through a series of vigorous tests before and after production. Each device can and must be put through a rigorous industry standard test methodology to verify the quality of the device. Simple test circuits can also be embedded in an IC device to test the functionality of different parts of the device. These test circuits are usually used to carry out post-production tests to ensure that the IC device is error free and is operating as expected.
Generally speaking, design for test (DFT) is a name for design techniques or embedded circuits that are used to detect various kinds of faults on a manufactured IC device. For instance, a DFT circuit can be used to detect stuck-at faults in a logic block on the IC device.
Scan chains, typically formed by connecting logic elements such as flip flops and other storage elements in series, are integrated into the device to test the device for various logic defects. A scan chain can be configured to receive a set of test vectors that can be used to test the functionality of the particular device. Typically, the device is allowed to operate using the set of test vectors for at least several clock cycles before the data from the scan chain is read to determine the functionality of the device.
In a typical scan test, two fast clock transitions are needed. The first transition launches the test value and the second transition captures the result based on the test value. Two of the more common scan test methods are launch-on-capture (LOC) and launch-on-shift (LOS). Even though LOC scan test is commonly used, the LOC scan test may not be able to capture every stage of registers in the scan chain at-speed. In this aspect, the LOS scan test may be a better option because all stages of registers can be tested at-speed with the LOS scan test. Even though the LOS scan test is a better scan technique as compared to the LOC scan test, in an LOS scan test, the scan enable signal that is used to put the scan chain into a “scan mode” needs to be routed as a clock, which generally requires more area on the IC device.